The present invention is related in general to the field of electronic systems and semiconductor devices and more specifically to the fabrication and processing of ultra-thin gate dielectric layers.
The trend in semiconductor technology to double the functional complexity of its products every 18 months (Moore""s xe2x80x9clawxe2x80x9d), which is still valid today after having dominated the industry for the last three decades, has several implicit consequences. First, the cost per functional unit should drop with each generation of complexity so that the cost of the product with its doubled functionality would increase only slightly. Second, the higher product complexity should largely be achieved by shrinking the feature sizes of the chip components while holding the package dimensions constant; preferably, even the packages should shrink. Third, the increased functional complexity should be paralleled by an equivalent increase in reliability of the product. And fourth, but not least, the best financial profit rewards were held out for the ones who were ahead in the marketplace in reaching the complexity goal together with offering the most flexible products for application.
The scaling of the components in the lateral dimension requires vertical scaling as well so as to achieve adequate device performance. This vertical scaling requires the thickness of the gate dielectric, commonly silicon dioxide (SiO2) to be reduced. Thinning of the gate dielectric provides a smaller barrier to dopant diffusion from a poly-silicon gate structure (or metal diffusion from a metal gate structure) through the underlying dielectric, often resulting in devices with diminished electrical performance and reliability. In ultra-thin dielectric layers, interfaces with their unwelcome electronic states and carrier traps may finally dominate the electrical characteristics.
One way of reducing these problems is to use silicon nitride as the gate dielectric layer instead of silicon dioxide. Silicon nitride has a higher dielectric constant than typical thermally grown SiO2 and provides greater resistance to impurity diffusion. However, the electrical properties of standard deposited silicon nitride films are far inferior to thermal oxides. One approach for silicon nitride films as gate insulators employs an oxide layer between the nitride layer and the substrate; see Xie-wen Wang et al., xe2x80x9cHighly Reliable Silicon Nitride Thin Films Made by Jet Vapor Depositionxe2x80x9d, Japan J. Appl. Phys., vol.34, pp. 955-958, 1995. Unfortunately, this technique has numerous practical shortcomings.
Another approach of maintaining the benefit of the electrical properties of the oxide film while also getting the barrier properties of a nitride film is to incorporate nitrogen into a gate oxide layer. In known technology, this is accomplished by a nitrided oxide process involving ammonia to penetrate the gate oxide at temperatures in excess of 1000xc2x0 C. Once the high temperature reaction has begun, it is difficult to control the concentration of the nitrogen incorporated into the gate oxide. Excessive nitrogen near the interface between the semiconductor substrate and the gate oxide can adversely affect the threshold voltage and degrade the channel mobility of the device due to charged interface traps associated with the nitrogen.
As described by S. V. Hattangady et al., xe2x80x9cControlled Nitrogen Incorporation at the Gate Oxide Surfacexe2x80x9d, Appl.Phys.Lett. vol. 66. p.3495, 1995, a high pressure and low power process provides nitrogen incorporation specifically at the gate/conductor interface. The long exposure time to the plasma increases the probability of charge-induced damage to the oxide and reduces the production throughput.
In U.S. Pat. No. 6,136,654, issued on Oct. 24, 2000 (Kraft et al., xe2x80x9cMethod of Forming Thin Silicon Nitride or Silicon Oxynitride Gate Dielectricsxe2x80x9d), the SiO2 (or oxynitride) layer is subjected to a nitrogen-containing plasma so that the nitrogen is either incorporated into the SiO2 layer or forms a nitride layer at the surface of the substrate. The source of nitrogen in the plasma is comprised of a material consisting of N2, NH3, NO, N2O, or mixtures thereof. This method provides a non-uniform nitrogen distribution in the SiO2 layer and is applicable to relatively thick oxide layers (1 to 15 nm) ; it is not suitable for ultra-thin SiO2 layers (0.5 to 2 nm).
An urgent need has, therefore, arisen for a coherent, low-cost method of plasma nitridation and re-oxidation and damage healing of ultra-thin gate oxide layers. The method should further produce excellent electrical device performance, mechanical stability and high reliability. The fabrication method should be simple, yet flexible enough for different semiconductor product families and a wide spectrum of design and process variations. Preferably, these innovations should be accomplished without extending production cycle time, and using the installed equipment, so that no investment in new manufacturing machines is needed.
An embodiment of the present invention is a method of forming an ultra-thin dielectric layer, the method comprising the steps of: providing a substrate having a semiconductor surface; forming an oxygen-containing layer on the semiconductor surface; exposing the oxygen-containing layer to a nitrogen-containing plasma to create a uniform nitrogen distribution throughout the oxygen-containing layer; and re-oxidizing and annealing the layer to stabilize the nitrogen distribution, heal plasma-induced damage, and reduce interfacial defect density.
This annealing step is selected from a group of four re-oxidizing techniques:
Consecutive annealing in a mixture of H2 and N2 (preferably less than 20% H2 ), and then a mixture of O2 and N2 (preferably less than 20% O2);
annealing by a spike-like temperature rise (preferably less than 1 s at 1000 to 1150xc2x0 C.) in nitrogen-comprising atmosphere (preferably N2/O2 or N2O/H2 );
annealing by rapid thermal heating in ammonia of reduced pressure (preferably at 600 to 1000xc2x0 C. for 5 to 60 s);
annealing in an oxidizer/hydrogen mixture (preferably N2O with 1% H2 ) for 5 to 60 s at 800 to 1050xc2x0 C.
Another embodiment of the present invention is a method of forming a transistor having a conductive gate structure disposed on an ultra-thin gate dielectric layer, the method comprising the steps of: Providing a substrate having a semiconductor surface; providing an ultra-thin oxygen-containing dielectric layer, preferably SiO2 or an oxynitride, on the semiconductor surface; subjecting the dielectric layer to a nitrogen-containing plasma so that a uniform nitrogen distribution is created throughout the oxygen-containing layer; subjecting the nitrided oxygen-containing layer to an annealing and re-oxidation step selected from techniques listed above; and wherein the gate dielectric layer is comprised of the annealed dielectric layer having the uniform and stabilized nitrogen distribution. Preferably, the conductive gate structure is comprised of doped poly-silicon or a metal. Forming the source, drain and contacts completes the transistor.
Another embodiment of the present invention is a method of forming a capacitor having a capacitor dielectric comprising the steps of: Providing a substrate having a semiconductor surface; forming a first electrode over the semiconductor surface; providing an ultra-thin dielectric layer on the first electrode, the dielectric layer comprised of an oxide, preferably SiO2 or an oxynitride; subjecting the dielectric layer to a nitrogen-containing plasma so that nitrogen is uniformly distributed throughout the layer; annealing the dielectric layer; forming a second electrode on the dielectric layer; wherein the capacitor dielectric layer is comprised of the annealed dielectric layer having the uniform and stabilized nitrogen distribution.
It is a technical advantage of the present invention that it is equally applicable to NMOS and PMOS transistors with ultra-thin gate oxides. The invention is well suited for the continuing trend of device miniaturization.
The technical advances represented by the invention, as well as the aspects thereof, will become apparent from the following description of the preferred embodiments of the invention, when considered in conjunction with the accompanying drawings and the novel features set forth in the appended claims.